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| (R) HIP6013 Data Sheet November 3, 2005 FN4325.1 Buck Pulse-Width Modulator (PWM) Controller The HIP6013 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive an N-Channel MOSFET in a standard buck topology. The HIP6013 integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter can be precisely regulated to as low as 1.27V, with a maximum tolerance of 1.5% over temperature and line voltage variations. The HIP6013 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The HIP6013 protects against over-current conditions by inhibiting PWM operation. The HIP6013 monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. Features * Drives N-Channel MOSFET * Operates From +5V or +12V Input * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio * Excellent Output Voltage Regulation - 1.27V Internal Reference - 1.5% Over Line Voltage and Temperature * Over-Current Fault Monitor - Does Not Require Extra Current Sensing Element - Uses MOSFET's rDS(on) * Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to Over 1MHz * 14 Ld, SOIC Package * Pb-Free Plus Anneal Available (RoHS Compliant) Applications Ordering Information PART NUMBER HIP6013CB PART TEMP. RANGE PKG. MARKING (C) PACKAGE DWG. # HIP6013CB 0 to 70 0 to 70 14 Ld SOIC M14.15 14 Ld SOIC M14.15 (Pb-free) * Power Supply for Pentium(R), Pentium Pro, PowerPCTM and AlphaTM Microprocessors * High-Power 5V to 3.xV DC-DC Regulators * Low-Voltage Distributed Power Supplies HIP6013CBZ 6013CBZ (See Note) Add "-T" suffix for tape and reel. Pinout HIP6013 (SOIC) TOP VIEW RT OCSET SS COMP FB EN GND 1 2 3 4 5 6 7 14 VCC 13 NC 12 NC 11 NC 10 BOOT 9 8 UGATE PHASE NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PowerPCTM is a trademark of IBM. AlphaTM is a trademark of Digital Equipment Corporation. Pentium(R) is a registered trademark of Intel Corporation. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP6013 Typical Application 12V +5V OR +12V VCC OCSET MONITOR AND PROTECTION EN BOOT RT OSC SS UGATE PHASE +VO HIP6013 REF + FB + COMP Block Diagram VCC POWER-ON RESET (POR) 10A + OCSET EN - OVERCURRENT 4V SOFTSTART SS BOOT UGATE PHASE 200A 1.27 VREF REFERENCE + PWM COMPARATOR - + INHIBIT PWM - GATE CONTROL LOGIC FB COMP ERROR AMP GND RT OSCILLATOR 2 4325.1 November 3, 2005 HIP6013 Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . +15.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Nominal Supply Shutdown Supply POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Enable - Input threshold Voltage Rising VOCSET Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude REFERENCE Reference Voltage ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate GATE DRIVERS Upper Gate Source Upper Gate Sink PROTECTION OCSET Current Source Soft Start Current Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ICC EN = VCC; UGATE and LGATE Open EN = 0V - 5 50 100 mA A VOCSET = 4.5VDC VOCSET = 4.5VDC VOCSET = 4.5VDC 8.8 0.8 - 1.27 10.4 2.0 - V V V V RT = OPEN, VCC = 12 6k < RT to GND < 200k VOSC RT = OPEN 180 -20 - 200 1.9 220 +20 - kHz % VP-P 1.251 1.270 1.289 V GBW SR COMP = 10pF - 88 15 6 - dB MHz V/s IUGATE RUGATE VBOOT - VPHASE = 12V, VUGATE = 6V ILGATE = 0.3A 350 - 500 5.5 10 mA IOCSET ISS VOCSET = 4.5VDC 170 - 200 10 230 - A A 3 4325.1 November 3, 2005 HIP6013 Typical Performance Curves 40 RT PULLUP TO +12V 35 CGATE = 3300pF 30 25 100 RT PULLDOWN TO VSS ICC (mA) 20 15 10 5 10 100 SWITCHING FREQUENCY (kHz) 1000 0 100 CGATE = 10pF CGATE = 1000pF 1000 RESISTANCE (k) 10 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) 900 1000 FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY Functional Pin Description RT OCSET SS COMP FB EN GND 1 2 3 4 5 6 7 14 VCC 13 NC 12 NC 11 NC 10 BOOT 9 8 UGATE PHASE SS (Pin 3) Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the softstart interval of the converter. COMP (Pin 4) and FB (Pin 5) COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. RT (Pin 1) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 5 * 10 Fs 200kHz + -----------------RT 6 EN (Pin 6) This pin is the open-collector enable pin. Pull this pin below 1V to disable the converter. In shutdown, the soft start pin is discharged and the UGATE and LGATE pins are held low. GND (Pin 7) (RT to GND) Signal ground for the IC. All voltage levels are measured with respect to this pin. Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation.: 4 * 10 Fs 200kHz - -----------------RT 7 PHASE (Pin 8) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. (RT to 12V) OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCS), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: I OCS * R OCSET I PEAK = ------------------------------------------r DS ( ON ) UGATE (Pin 9) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. BOOT (Pin 10) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. VCC (Pin 14) Provide a 12V bias supply for the chip to this pin. An over-current trip cycles the soft-start function. 4 4325.1 November 3, 2005 HIP6013 Functional Description Initialization The HIP6013 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages and the enable (EN) pin. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). With the EN pin held to VCC, the POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. The Power-On Reset (POR) function inhibits operation with the chip disabled (EN pin low). With both input supplies above their POR thresholds, transitioning the EN pin high initiates a soft start interval. SOFT-START (1V/DIV) 0V 0V t1 t2 OUTPUT VOLTAGE (1V/DIV) t3 TIME (5ms/DIV) FIGURE 3. SOFT-START INTERVAL Over-Current Protection The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, rDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200A (typical) current sink develops a voltage across ROCSET that is reference to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, the over-current function initiates a softstart sequence. The soft-start function discharges CSS with a 10A current sink and inhibits PWM operation. The softstart function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 4 is 2.5W. Soft Start The POR function initiates the soft start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter's output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator's triangle wave. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the reference voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. 5 4325.1 November 3, 2005 HIP6013 VIN SOFT-START 4V 2V 0V 15A 10A D2 5A 0A RETURN TIME (20ms/DIV) HIP6013 UGATE PHASE CIN Q1 LO VOUT LOAD VOUT LOAD OUTPUT INDUCTOR CO FIGURE 4. OVER-CURRENT OPERATION FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET * R OCSET I PEAK = -------------------------------------------------r DS ( ON ) where IOCSET is the internal OCSET current source (200A - typical). The OC trip point varies mainly due to the MOSFET's rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine I PEAK for I PEAK > I OUT ( MAX ) + ( I ) 2 , where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 6 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6013 within 3 inches of the MOSFETs, Q1. The circuit traces for the MOSFETs' gate and source connections from the HIP6013 must be sized to handle up to 1A peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. +VIN BOOT CBOOT D1 Q1 LO Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. HIP6013 SS PHASE VCC +12V CVCC D2 CO CSS GND FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES 6 4325.1 November 3, 2005 HIP6013 Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (Vout) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of Vin at the PHASE node. The PWM wave is smoothed by the output filter (Lo and Co). VIN OSC PWM COMPARATOR VOSC + DRIVER LO DRIVER PHASE CO ESR (PARASITIC) ZFB VE/A + ERROR AMP VOUT Modulator Break Frequency Equations 1 F LC = -------------------------------------2 * L O * C O 1 F ESR = ------------------------------------------2 * ( ESR * C O ) - The compensation network consists of the error amplifier (internal to the HIP6013) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180o. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: Compensation Break Frequency Equations 1 F Z1 = --------------------------------2 * R2 * C1 1 F Z2 = ---------------------------------------------------2 * ( R1 + R3 ) * C3 1 F P1 = ----------------------------------------------------C1 * C2 2 * R2 * --------------------- C1 + C2 1 F P2 = --------------------------------2 * R3 * C3 - ZIN REFERENCE 1. Pick Gain (R2/R1) for desired converter bandwidth DETAILED COMPENSATION COMPONENTS ZFB C2 C1 R2 C3 R1 ZIN R3 VOUT 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC) 3. Place 2ND Zero at Filter's Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier's Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 8 shows an asymptotic plot of the DC-DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak do to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45o. Include worst case component variations when determining phase margin. COMP + FB HIP6013 REF FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN The modulator transfer function is the small-signal transfer function of Vout/VE/A. This function is dominated by a DC Gain and the output filter (Lo and Co), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (Vin) divided by the peak-to-peak oscillator voltage VOSC. 7 4325.1 November 3, 2005 HIP6013 100 80 60 GAIN (dB) 40 20 0 -20 -40 FLC -60 10 100 1K 10K FESR 100K 1M 10M MODULATOR GAIN 20LOG (R2/R1) OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2 component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT I = ------------------------------- * --------------Fs x L O V IN V OUT = I x ESR 20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN FREQUENCY (Hz) FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6013 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = LO x ITRAN VIN - VO tFALL = LO x ITRAN VO Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium-Pro be composed of at least forty (40) 1.0F ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the anode of Schottky diode D2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable 8 4325.1 November 3, 2005 HIP6013 operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. Standard-gate MOSFETs are normally recommended for use with the HIP6013. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET's absolute gate-tosource voltage rating determine whether logic-level MOSFETs are appropriate. Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. A logic-level MOSFET can only be used for Q1 if the MOSFET's absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. Figure 10 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET is a good choice for Q1 under these conditions. +12V DBOOT +5V OR +12V VCC BOOT CBOOT UGATE PHASE Q1 NOTE: VG-S VCC - VD MOSFET Selection/Considerations The HIP6013 requires an N-Channel power MOSFET. It should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for the MOSFET. Switching losses also contribute to the overall MOSFET power loss (see the equations below). These equations assume linear voltagecurrent transitions and are approximations. The gatecharge losses are dissipated by the HIP6013 and don't heat the MOSFET. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that the MOSFET is within its maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. PCOND = IO2 x rDS(ON) x D 1 PSW = 2 IO x VIN x tSW x Fs Where: D is the duty cycle = VO / VIN, tSW is the switching interval, and Fs is the switching frequency. HIP6013 D2 + GND FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION 9 4325.1 November 3, 2005 HIP6013 +12V +5V OR LESS VCC BOOT HIP6013 Q1 UGATE PHASE NOTE: VG-S VCC - 5V D2 + Schottky Selection Rectifier D2 conducts when the upper MOSFET Q1 is off. The diode should be a Schottky type for low power losses. The power dissipation in the Schottky rectifier is approximated by: PCOND = IO x Vf x (1 - D) Where: D is the duty cycle = VO /VIN, and Vf is the schottky forward voltage drop In addition to power dissipation, package selection and heatsink requirements are the main design tradeoffs in choosing the Schottky rectifier. Since the three factors are interrelated, the selection process is an iterative procedure. The maximum junction temperature of the rectifier must remain below the manufacturer's specified value, typically 125oC. By using the package thermal resistance specification and the Schottky power dissipation equation (shown above), the junction temperature of the rectifier can be estimated. Be sure to use the available airflow and ambient temperature to determine the junction temperature rise. GND FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION 10 4325.1 November 3, 2005 HIP6013 HIP6013 DC-DC Converter Application Circuit The figure below shows a DC-DC converter circuit for a microprocessor application, originally designed to employ the HIP6007 controller. Given the similarities between the HIP6007 and HIP6013 controllers, the circuit can be implemented using the HIP6013 controller without any modifications. However, given the expanded reference voltage tolerance range, the HIP6013-based converter may require additional output capacitance. Detailed information on the circuit, including a complete Bill-of-Materials and circuit board description, can be found in application note AN9722. See Intersil's home page on the web: http://www.intersil.com. 12VCC VIN C1-5 3x 680F RTN C17-18 2x 1F 1206 R7 10K ENABLE C12 1F 1206 6 SS 3 RT 1 C19 VCC 14 MONITOR AND PROTECTION 2 OCSET 10 BOOT Q1 OSC U1 9 UGATE 8 PHASE 13 NC + 4 + 7 GND JP1 12 NC 11 NC COMP CR3 C6-11 4x 1000F RTN C20 0.1F L2 VOUT 1000pF R6 3.01K CR1 4148 PHASE TP2 C13 0.1F R1 SPARE REF HIP6013 FB 5 R2 1K C15 0.01F C16 R3 1K SPARE C14 33pF R5 15K COMP TP1 R4 SPARE Component Selection Notes: C1-C3 - 3 each 680F 25W VDC, Sanyo MV-GX or equivalent. C6-C9 - 4 each 1000F 6.3W VDC, Sanyo MV-GX or equivalent. L1 - Core: Micrometals T60-52; Winding: 14 Turns of 17AWG. CR1 - 1N4148 or equivalent. CR3 - 15A, 35V Schottky, Motorola MBR1535CT or equivalent. Q1 - Intersil MOSFET; RFP25N05. FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 4325.1 November 3, 2005 |
Price & Availability of HIP601305
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